The disclosed embodiments relate to methods and apparatus for controlling electrolyte hydrodynamics during electroplating. More particularly, methods and apparatus described herein are particularly useful for plating metals onto semiconductor wafer substrates, such as through resist plating of small microbumping features (e.g., copper, nickel, tin and tin alloy solders) having widths less than, e.g., about 50 μm, and copper through silicon via (TSV) features.
Electrochemical deposition processes are well-established in modern integrated circuit fabrication. The transition from aluminum to copper metal line interconnections in the early years of the twenty-first century drove a need for increasingly sophisticated electrodeposition processes and plating tools. Much of the sophistication evolved in response to the need for ever smaller current carrying lines in device metallization layers. These copper lines are formed by electroplating the metal into very thin, high-aspect ratio trenches and vias in a methodology commonly referred to as “damascene” processing (pre-passivation metalization).
Electrochemical deposition is now poised to fill a commercial need for sophisticated packaging and multichip interconnection technologies known generally and colloquially as wafer level packaging (WLP) and through silicon via (TSV) electrical connection technology. These technologies present their own very significant challenges due in part to the generally larger feature sizes (compared to Front End of Line (FEOL) interconnects) and high aspect ratios.
The technologies involve electroplating on a significantly larger size scale than damascene applications. Depending on the type and application of the packaging features (e.g., through chip connecting TSV, interconnection redistribution wiring, or chip to board or chip bonding, such as flip-chip pillars), plated features are usually, in current technology, greater than about 2 micrometers and typically 5-300 micrometers (for example, pillars may be about 50 micrometers). For some on-chip structures such as power busses, the feature to be plated may be larger than 300 micrometers. The aspect ratios of the WLP features are typically about 1:1 (height to width) or lower, while TSV structures can have very high aspect ratios (e.g., in the neighborhood of about 20:1).
Given the relatively large amount of material to be deposited, not only feature size, but also plating speed differentiates WLP and TSV applications from damascene applications. For many WLP applications, plating must fill features at a rate of at least about 2 micrometers/minute, and typically at least about 4 micrometers/minute, and for some applications at least about 7 micrometers/minute. At these higher plating rate regimes, efficient mass transfer of metal ions in the electrolyte to the plating surface is important.
Higher plating rates present challenges with respect to uniformity of the electrodeposited layer, that is, plating must be conducted in a highly uniform manner.